Design and Implementation of a Digital System with Verilog Modules: Frequency Divider, Up/Down Counter (Mod 100), and 7-Segment Drivers

The task is design and implementation of a digital system shown in the figure. The project consists of three
major modules (Verilog): Frequency divider, Up/Down Counter (Mod 100), 7-Seg Drivers.
The frequency divider receives 5 MHz from Clock 50 (PIN_AF14) and divides is to 50000 to generate 1 Hz
frequency at the output (The code is provided).
The Mod 100 counter counts with 1 Hz frequency. The counter direction is determined by SW0 (SW0=0:
Counts up, SW0=1: counts down). Also, Key0 (Push Bottom is used for resetting: If Key0 pressed (Key0 = 0)
the counter resets and start counting once the Key is released (Key0 = 1). For the counter Verilog code, you
can refer to the “Verilog Resources” posted in Canvas (Project).
The 7-seg driver is the same module that you have made in Lab 4.
Clock_50 Frequenc
(PIN_AF14) —>] au y
50 MHz Divider
CLK
(1 Hz)
4 bits
(BDO) [ 7-5eg | 7bits y 7-Seg
Mod 100 counter Deriver (Hex0)
. 4 bits
(2-digit BCD counter) | ep) ro INET
(0 ~ 99) Deriver (Hex1)
Tp/Down Reset
0 1
SWO (PIN_AB12) KeyO (PIN_AA14)
1) =0: Up Count 1) Pressed (0): Counter resets (=0)
2) = 1: Down Count 2) Released (1): Counter counts